Programmable Logic Design Engineer
Viasat INC - Germantown, Maryland; Carlsbad, California; Independence, Ohio; Englewood, Colorado
Posted Apr 29, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Programmable Logic Design Engineer Germantown, Maryland; Carlsbad, California; Independence, Ohio; Englewood, Colorado About us One team. Global challenges. Infinite opportunities. At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We're looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team. What you'll do In this role you will help develop high speed signal processing algorithms and/or network protocols in FPGAs. The individual will be responsible for the full design phase starting from the requirements' phase to documentation, block diagrams, implementation of source code, simulation, place & route, testing in hardware, and integration. The day-to-day Collaborate with team members to jointly develop high-speed digital signal processing and waveform processing algorithms supporting satellite communications applications Develop testbenches and help maintain and update system level verification environment Synthesize Verilog and System Verilog for Xilinx/AMD FPGAs Develop timing constraints, analyze timing results, and implement design changes required to close timing Generate and collaborate on required design documents, development requirements, specifications and verification protocols Responsible for owning and driving technical issues to resolution Integrate and debugs design in the laboratory What you'll need Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field 5-8 years FPGA design experience, including Xilinx Vivado Strong knowledge of System Verilog Experience with RTL design for various signal processing blocks, including but
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Apply link verified; last checked Jun 13, 2026.
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