Staff, FPGA Digital Design Engineer

Verified benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Verified

No last checked 2026-05-07T13:50:00Z

Salary

Not disclosed

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Staff, FPGA Digital Design Engineer Germantown, MD USA Summary: VIAVI (NASDAQ: VIAV) is a global provider of network test, monitoring and assurance solutions for telecommunications, cloud, enterprises, first responders, military,

Read the full description at viavisolutions.wd1.myworkdayjobs.com. FewerJobs shows a short excerpt and links to the source.