SI Simulation Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

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Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

SI Simulation Engineer Taipei About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you'll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities - Perform pre-layout and post-layout signal integrity simulation for high-speed interfaces, including DDR4/DDR5, PCIe Gen3-Gen5, and 100G/400G/800G Ethernet. - Evaluate channel loss, PCB material, stack-up, IC placement, and routing constraints during the early design stage. - Build and analyze end-to-end channel models, including PCB traces, vias, connectors, cables, packages, and IC models. - Optimize high-speed channel structures, including vias, anti-pads, connector launches, cables, and routing topology. - Analyze insertion loss, return loss, crosstalk, impedance discontinuity, jitter, eye diagram, and BER performance. - Define PCB layout guidelines and routing constraints for high-speed interfaces. - Work with EE, layout, mechanical, vendor, and validation teams to review designs and resolve SI issues. - Support simulation-to-measurement correlation using VNA, TDR, oscilloscope, BERT, or compliance test results. Qualifications - Bachelor's degree or above in Electrical Engineering, Electronics Engineering, or a related field. - 5+ years of experience in high-speed signal integrity simulation

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