ASIC Engineering Layout Leader | Custom IC layout, Analog, Mixed-signal, and high-speed designs | 12+ years, Bangalore

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

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Seniority

Mid From the posting source

Schedule

Shift type

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Weekend work

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Application

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Assessment

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Deadline

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Where they hire

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About this role

ASIC Engineering Layout Leader | Custom IC layout, Analog, Mixed-signal, and high-speed designs | 12+ years, Bangalore Bangalore, India Exciting opportunity for an ASIC Engineering Layout Leader and drive the development of next-generation high-performance analog and mixed-signal designs. Lead end-to-end layout development, optimize designs for manufacturability, and collaborate with cross-functional teams to deliver innovative solutions in high-speed networking. Shape the future of optical interconnect with Cisco Systems.

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.