ASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune)

Benefits

Parental leave

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Market context

Median wage (BLS OEWS)

$111,944 national median

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

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Weekend work

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Application

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Deadline

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About this role

ASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune) Pune, India Exciting opportunity for a Digital Design Lead to drive the development of advanced digital logic for high-speed optical interconnects at Cisco. Lead technical strategy, manage ASIC/SoC design, and collaborate with cross-functional teams to deliver cutting-edge solutions for next-generation data center networking. Join us to shape the future of optical technology.

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a source-linked preview and links to the original posting.