Semiconductor Design Engineer [Teradyne, N. Reading, MA]

Verified benefits

Parental leave

4 weeks source

Non-birth-parent leave

4 weeks

Verified

Yes last checked 2026-05-07

Salary

$141K-$225K

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

175% above the BLS national median for design aggregate.

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Semiconductor Design Engineer [Teradyne, N. Reading, MA] We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology

Read the full description at jobs.teradyne.com. FewerJobs shows a source-linked preview and links to the original posting.