Staff Engineer, CPU Architectural Verification
TensTorrent - Austin, Texas, United States; Santa Clara, California, United States
Posted Apr 21, 2026
Benefits
- Parental leave
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- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Salary
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- 401(k) match
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Schedule
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- Weekend work
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Application
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Where they hire
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About this role
Staff Engineer, CPU Architectural Verification Austin, Texas, United States; Santa Clara, California, United States Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will own CPU architectural verification, shaping how our out-of-order RISC-V CPUs are validated against architectural intent, ISA behavior, privileged architecture requirements, and system-visible correctness across the verification stack. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are - You bring 8+ years in CPU architectural verification, CPU design verification, or closely related CPU validation work. - You understand CPU ISA behavior, privileged architecture, exception handling, memory ordering, and high-performance out-of-order CPU microarchitecture in depth. - You are comfortable debugging architectural mismatches using
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