Senior Physical Design Engineer
TensTorrent - Tokyo, Japan
Posted Apr 20, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
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- Salary
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Market context
- Median wage (BLS OEWS)
- $116,543 national median
- Projected growth (BLS Employment Projections)
- +9.8% - Much faster than average
Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Senior Physical Design Engineer Tokyo, Japan Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a senior physical design engineer to join Tenstorrent's AIDC Yayoi project, driving chiplet-level and chip-top physical implementation of high-performance CPU-based SoCs in a cutting-edge system-in-package environment. This role is hybrid, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are - You have a Bachelor's, Master's, or PhD in electrical engineering, computer engineering, or computer science, with extensive experience (typically 10+ years) in SoC/ASIC/GPU/CPU physical design on taped-out designs. - You are highly skilled with industry-standard tools (e.g., Synopsys/Cadence) and physical verification, and comfortable scripting in TCL and at least one other language (e.g., Python). - You are a strong collaborator who can guide and mentor junior engineers, communicate clearly with global
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