FewerJobs.
All jobs

Design FAE Manager - EDA and IP

Silvaco Group Inc - Shanghai, Shanghai, China

Posted Jun 10, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
Not verified
Relocation assistance
Not verified
Childcare support
Not verified
Learning budget
Not verified
Verification
Not verified
Salary
Not verified

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)
$66,396 U.S. median for this role
Projected growth (BLS Employment Projections)
+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Design From the posting source
Seniority
Senior From the posting source

Schedule

Shift type
Not verified
Weekend work
Not verified

Company

Equity
Offered Verified - SEC 10-K source

Application

Cover letter
Not verified
Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Design FAE Manager - EDA and IP Shanghai, Shanghai, China Company Description: About Silvaco: Silvaco is a publicly traded company on the Nasdaq market under the symbol SVCO. For over three decades, Silvaco, based in Silicon Valley, California and with global locations around the world has solved semiconductor design challenges by offering affordable and competitive TCAD (Technology Computer Aided Design) software, EDA (Electronic Design Automation) software, proven design IP (intellectual property), and world class support to engineers and researchers across the globe. Silvaco solutions span from atoms to systems: starting with simulation of material behavior impacting semiconductor devices, to design and analysis of transistor circuits, and lastly providing IP blocks for systems-on-chip (SoC) designs. Job Description: As a EDA & IP Field Application Engineer Lead, you are responsible for providing pre-sales and post-sales technical support for our EDA tools and IPs to our customers. The responsibilities include: 作为应用工程师主管,负责对公司客户的EDA工具及IP的售前和售后的技术支持,岗位职责如下: Discovering new project or new customer from technology point of view, discussing with customers on their application, proposing Silvaco solutions to best-fit customer requirements 从技术角度发掘新的项目或客户,与客户探讨其技术要求,提供适合客户需求的Silvaco的解决方案 Work with sales team to grow business, achieve high customer satisfaction and strong customer relationship 与销售团队紧密合作,推动业务增长,提升客户的满意度,建立良好的客户关系 Mentor FAE engineers 指导和带领其它 FAE团队成员一起支持所有客户项目 Work with the R&D team to enhance the capability of Silvaco tools and quickly respond to the customer's new technical requirements 与研发团队紧密合作,增强Silvaco工具的优势,快速响应客户新的技术需求 Business travel required 需要不定期出差 Qualifications: MS or PhD in Microelectronics, Electronic Engineering, Computer Science etc. 微电子、电子工程、计算机等专业硕士及以上学历 5+ years of Standard Cell Library or SRAM design experience preferable in advanced process nodes. 5年以上先进工艺节点的标准单元库或者SRAM设计经验 Proficient in

Read the full description at jobs.smartrecruiters.com. FewerJobs shows a preview and links to the original posting.

Apply at jobs.smartrecruiters.com

Apply link not verified; last-live date unavailable.

What verified means

Verified means a displayed claim has field-level provenance to a source FewerJobs pulled: a government or employer source, or the original job posting. Posting-sourced facts are employer-stated and are labeled separately from government records.

Related jobs