Senior/Staff/ Sr Staff Engineer, IP/SoC Design Verification

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Senior From the posting source

Schedule

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Weekend work

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Application

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Assessment

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Deadline

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Where they hire

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About this role

Senior/Staff/ Sr Staff Engineer, IP/SoC Design Verification Bengaluru, KA, India Company Description: Responsibilities: Be a part of end‑to‑end verification execution for SOC owning complex digital IP's and subsystems from specification to sign‑off Define and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria Develop scalable, reusable UVM‑based verification environments for IP and subsystem verification Lead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics Apply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency Drive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration Review IP specifications and work with architects to translate requirements into robust verification plans and checkers Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors Work with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools Mentor junior engineers and promote best‑in‑class verification practices and continuous improvement Support Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required. Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration. Qualifications Bachelor's or Master's degree in electronics Engineering 5-12 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits. Strong expertise in UVM‑based testbench architecture and development Proven experience in metric‑driven verification, including functional and code coverage closure Deep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices Experience with directed and constrained‑random verification methodologies

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