Senior Analog Engineering Manager

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source

Seniority

Senior From the posting source

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Senior Analog Engineering Manager Morrisville, NC, United States Company Description: We are seeking a Senior Analog Engineering Manager to lead the development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs. This role requires deep technical expertise in high-speed memory interfaces, combined with strong people leadership and program ownership. The successful candidate will manage a team responsible for end-to-end delivery of high-performance, low-power DDR PHYs, from architecture through silicon bring-up, while shaping the roadmap for DDR6-class signaling and architecture Job Description: Technical Leadership (DDR5 / DDR6) Own and guide the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures. Provide technical oversight for critical analog and mixed-signal blocks, including: High-speed TX/RX datapaths Advanced equalization, termination, and training circuits DLL/PLL-based clocking solutions for multi-GHz operation Voltage, reference generation, and power-aware IO design Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive DDR5/DDR6 data rates. Ensure compliance with JEDEC DDR5 specifications and alignment with evolving DDR6 standards and industry direction. Lead post-silicon bring-up, characterization, debug, and yield improvement, including lab and customer-system correlation. People & Organization Leadership Build, lead, and mentor a team of analog and mixed-signal designers focused on high-speed memory interfaces. Set technical direction, performance expectations, and development plans for senior and principal engineers. Drive hiring, onboarding, and team scaling aligned with DDR5 production and DDR6 development needs. Foster a culture of technical rigor, ownership, and execution excellence. Program & Cross-Functional Execution Own DDR5/DDR6 PHY execution balancing schedule, quality, and risk Partner closely

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