Principal Digital Verification Engineer
Renesas Electronics - Plano, TX, United States
Posted Jun 10, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
- Not verified
- Relocation assistance
- Not verified
- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Not verified checked Jun 7, 2026
- Salary
- Not verified
- 401(k) match
- Reported from DOL Form 5500 industry filing (not employer-specific)
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Market context
- U.S. role benchmark (BLS OEWS)
- $111,944 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +13.7% - Much faster than average
Matched to SOC 15-1252 - Data and ML aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Principal Digital Verification Engineer Plano, TX, United States Company Description: Renesas is looking for a talented individual for their memory interface products. These memory interface products mainly go to datacenters for AI and cloud computing, providing the highest bandwidth for intensive computing while consuming low power. This exciting role is responsible for the development of digital sections of leading-edge memory data buffer chips for DDR5, DDR6 and beyond. Job Description: · Verification of DDR5 Data Buffer to meet functional and performance specifications. · Be able to integrate and test on System-level and block level using UVM methodology. · Participate in feasibility studies. · Support in developing verification plan based on specifications. · Support in Verification planning, maintenance, feature extraction, verification tests, coverage and checker development. · Develop efficient, reusable state-of-the-art verification environments and testbench structures. · Optimize solutions for key indicators such as reusability, performance and ease of use · Identify and communicate improvements that may ease verification and/or improve design behavior. · Support in optimizing UVM based testbench. · Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User. Key Responsibilities · Drive the Memory interface products verification effort, including defining the verification strategy, developing test plans, coverage, and executing tests. · Technically work with a team of verification engineers, providing technical guidance and mentoring as needed. · Drive and quality control the creation of a verification test plan. · Work closely with the design team to ensure that the design meets the
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