Intern Verification Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

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Seniority

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Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Intern Verification Engineer Lviv, , Ukraine Company Description: Job Description: We are looking for a highly motivated Intern/ Working Student who will join our team as an Intern Verification Engineer in Lviv office. The role: Develop verification strategy for digital and mixed-signal IC designs. Verification planning, maintenance, feature extraction, verification tests, coverage and checker development. Develop reusable verification testbench structures following object-oriented programming principles and methodologies including UVM. Demonstrates an ability to learn new tool features and procedures. Attend training courses. Build up your knowledge and improve your skills using your own research. Qualifications: University student at Electrical Engineering, Computer Engineering, Computer Science or related disciplines. Preferably university experience in analog/digital design or test engineering. Knowledge of electrical properties, digital circuits, behavioral modeling and simulation and Unix. Ability to debug the HW issues. Ability to prioritize work, set goals and meet deadlines. Self-motivated and take full responsibility for solutions. Good written, communication and teamwork skills. Pre-Intermediate English. Will be a plus: Understanding of HW or FPGA design workflow. Knowledge of transistor-level integrated circuits and semiconductor physics, PCB design, FPGA, Microcontrollers, Arduino. Experience with protocols (UART, I2C, SPI, JTAG, etc.). Programming/scripting (Verilog/VHDL, SystemC/Verilog, TCL, Python, Bash, Perl, C/C++). Understanding of advanced verification methodologies (e.g. UVM, ABV). Familiarity with synthesis, P&R, static timing analysis (STA), assertion-based verification and formal verification. Experience in constrained random verification and metric driven verification. Additional Information: Fixed-Term Contract - duration approx. 6 months. Friendly and highly professional team. 14 calendar days paid vacation. Flexible working hours. Professional

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