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Design Verification, Forward Deployed Engineering

OpenAI - San Francisco, California, United States, London, UK

Posted May 8, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
Not verified checked Jun 7, 2026
Salary
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401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$66,396 U.S. median for this role
Projected growth (BLS Employment Projections)
+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Design From the posting source checked Jun 20, 2026
Seniority
Senior From the posting source checked Jun 20, 2026

Schedule

Shift type
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Weekend work
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Application

Cover letter
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Assessment
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Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Design Verification, Forward Deployed Engineering San Francisco, California, United States, London, UK About the Team OpenAI's Forward Deployed Engineering team partners with leading semiconductor companies to deploy production-grade AI systems across the entire chip design lifecycle: design, verification, and physical design. We operate at the intersection of customer delivery and core platform development, embedding deeply with customers to translate frontier model capabilities into systems that materially reduce design cycles, improve verification quality, and accelerate innovation. Our work turns early, high-touch deployments into reusable solution patterns, evaluation practices, and technical playbooks that scale across the semiconductor ecosystem. About the Role We are seeking an experienced Design Verification Engineer to join our semiconductor-focused Forward Deployed Engineering team. This is an IC role that will begin with a strong emphasis on design verification expertise, evaluation curation, and technical leverage across deployments, with the expectation that the person will grow into a broader Forward Deployed Engineering role over time. In the near term, you will serve as a senior technical SME for verification workflows: helping FDEs, Product, and Research teams understand how DV work is done in practice, pressure-testing AI-assisted verification ideas against real engineering workflows, and raising the quality of our solutions through deep domain judgment. You will help the broader team build fluency in verification methodology, tooling, and trade-offs. Over time, we expect this role to expand beyond SME support into broader FDE ownership: partnering directly with customers, shaping deployment strategy, building and iterating production-grade AI systems, driving technical workstreams, and helping

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