Design Verification Engineer

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About this role

Design Verification Engineer San Francisco, California, United States About the Team: OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We're looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems-ranging from individual IP blocks to subsystems and full SoC-working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. In this role you will: - Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. - Define verification plans based on architecture and microarchitecture specs. - Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. - Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. - Drive bug triage, root cause analysis, and work closely with design teams on resolution. - Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.

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