Principal FPGA/ASIC Engineer - Level 3

Verified benefits

Parental leave

6 weeks source

Non-birth-parent leave

6 weeks

Verified

Yes last checked 2025-01

Salary

$79K-$119K

401(k) match

Not verified

Market context

Median wage (BLS OEWS)

$116,543 national median

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

15% below the BLS national median for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Principal FPGA/ASIC Engineer - Level 3 United States-Arizona-Gilbert RELOCATION ASSISTANCE: No relocation assistance available CLEARANCE REQUIRED FOR START: No CLEARANCE TYPE: None TRAVEL: Yes, 10% of the Time Description At

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