FPGA Design Engineer (Level 3 or 4)

Verified benefits

Parental leave

6 weeks source

Non-birth-parent leave

6 weeks

Verified

Yes last checked 2025-01

Salary

$120K-$224K

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

159% above the BLS national median for design aggregate.

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

FPGA Design Engineer (Level 3 or 4) United States-Maryland-Linthicum RELOCATION ASSISTANCE: No relocation assistance available CLEARANCE REQUIRED FOR START: No CLEARANCE TYPE: Top Secret TRAVEL: Yes, 10% of the Time

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