Software Engineer, ASIC

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

$123K-$216K not verified - source not recorded; timestamp not recorded

401(k) match

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

45% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Software Engineer, ASIC South San Francisco, California, United States About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Infrastructure Team builds the foundation that enables the company to operate safely, robustly, and move at light-speed. We run a mixture of cloud-based and on-prem systems and have a user base spanning from highly technically proficient engineers to non-technical scientists and doctors; but all of them need solid systems, rugged networking, and bullet-proof software to do their jobs. Job Responsibilities and Description: As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span all layers of the work environment stack, from deployment of physical hardware on the manufacturing line, to custom tooling to stream neural recordings from implants. You will: - Build and maintain scalable EDA compute infrastructure for analog and digital chip design - Develop distributed simulation clusters to accelerate circuit verification at scale - Manage and optimize license infrastructure across multiple EDA vendors - Architect high-performance and robust shared storage for terabyte-scale design data - Develop build-system infrastructure and tooling for firmware targeting custom ASICs - Automate bare-metal server provisioning and lifecycle management for EDA compute fleets - Enhance developer experience for IC design and firmware engineers through monitoring, self-service tooling, and robust automation Tech Stack: - Rust, Python, Go - Cadence Virtuoso,

Read the full description at boards.greenhouse.io. FewerJobs shows a source-linked preview and links to the original posting.