Staff ASIC Verification Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified

Salary

$105K-$163K From the posting source checked Jun 20, 2026

401(k) match

Not verified

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

15% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Staff Plus From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Staff ASIC Verification Engineer Carlsbad, CA, US Responsibilities MaxLinear is seeking a Staff ASIC Verification Engineer to join our team. In this role, you will focus on the following: Define SoC verification strategies, test plans, and execution plan with ASIC Verification team Own IP level ASIC verification efforts toward SOC T/O Implement best industry practices for SoC verification; improve and harmonize verification methodologies across the organization to maximize efficiency and predictability of outcome Deliver test bench architecture, functional models, complete test environments, and test suites meeting coverage targets to ensure first-time silicon success Collaborate with design team and project stakeholders on testability improvements and on debug process during test bench bring up Qualifications Track record in verification strategy development and execution for large SoCs and signoff with coverage metrics Hands-on knowledge of UVM methodology, System Verilog, C/C++ Implementation of directed and constrained random test benches for communication physical layer, Ethernet networking, packet processing, PCIE and multi-CPU environments Knowledge of verification IP and functional coverage techniques Experience with gate level simulations of delay annotated netlists Exposure to FPGA emulation and lab validation Self-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast-paced environment BS in Electrical Engineering or related + 5 years of experience, or MS + 3 years of e

Read the full description at careersus-maxlinear.icims.com. FewerJobs shows a preview and links to the original posting.