Principal Systems Engineer, Storage Accelerator

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

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Learning budget

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Verification

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Salary

$155K-$193K From the posting source checked Jun 20, 2026

401(k) match

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

49% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Principal From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Principal Systems Engineer, Storage Accelerator Carlsbad, CA, US Responsibilities MaxLinear is seeking a Principal Systems Engineer, Storage Accelerator to join our team. You will be responsible for architecting and developing cutting-edge hardware platforms optimized for high-performance storage accelerator solutions. This role demands deep expertise in PCIe Gen5/Gen6 protocols, hands-on debugging, and board-level design of PCIe, OCP, and EDSFF form factors. You will drive architecture, design, validation, compliance with industry standards, and support of at scale manufacturing. In this role, you will focus on the following: PCIe Gen5/6 Protocol Expertise & Debugging Serve as the subject matter expert on PCIe Gen5 and Gen 6 protocols and physical layer implementation Conduct hands-on debugging and root-cause analysis for development and field issues Provide guidance on emerging interface technologies such as CXL, UALink, and other high-speed interconnects Hardware Design & Development Lead the design and development of PCIe HHHL, OCP 3.0 NIC, and EDSFF form factor boards for high-volume production Architect and implement high-speed interface designs, including PCIe Gen5 and OCP-compliant protocols Perform comprehensive Power Integrity (PI) and Signal Integrity (SI) analysis to ensure robust board-level performance Testing & Validation Drive Design Validation Testing (DVT) and Production Validation Testing (PVT) processes Develop and execute thermal test plans in collaboration with an internal team as well as third-party thermal labs Comp

Read the full description at careersus-maxlinear.icims.com. FewerJobs shows a preview and links to the original posting.