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Formal Verification Engineer

MatX - Mountain View, CA

Posted May 19, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
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  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
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Salary
$120K-$212K From the posting source checked Jun 20, 2026
401(k) match
Reported not verified - source URL not recorded; timestamp not recorded

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

43% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
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Weekend work
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Company

Equity
Offered From the posting source checked Jun 20, 2026

Application

Cover letter
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Assessment
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Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Formal Verification Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. We build the full stack-from silicon and rack design through compilers, kernels, and ML models. We are seeking a Formal Verification Engineer to bring rigorous mathematical guarantees to our hardware and software at every layer of the stack. What You'll Do Here - Apply model checking and formal property verification to RTL blocks, memory subsystems, and interconnects, providing complete coverage wherever possible, using tools such as JasperGold or VC-Formal. - Develop and maintain machine-checked proofs for critical compiler transformations, ensuring correctness of lowering passes from our high-level programming model down to hardware - Build embeddings of our hardware description languages and simulator models into interactive theorem provers (e.g. Lean 4, Rocq, Isabelle/HOL), and use those embeddings to prove functional correctness and microarchitectural properties directly against the designs - Collaborate with architecture, compiler, and silicon verification teams to identify correctness properties worth proving and translate them into tractable proof obligations - Drive methodology for integrating formal tools (JasperGold, SymbiYosys, or equivalent) into our existing practices Who You Are - Hands-on experience with hardware model checking-writing SVA/PSL properties, running bounded or unbounded proofs, and closing out formal verification targets at block or subsystem level - Practical experience with at least one interactive theorem prover (Lean, Coq, Isabelle/HOL, Agda, or similar) - Experience embedding an existing

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