FPGA Firmware Design Engineer

Verified benefits

Parental leave

4 weeks source

Non-birth-parent leave

4 weeks

Verified

Yes last checked 2026-05-07

Salary

Not disclosed

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

FPGA Firmware Design Engineer Arlington, VA FPGA Firmware Design Engineer /job/Arlington-VA/FPGA-Firmware-Design-Engineer_R-00181286 Arlington, VA Posted 16 Days Ago

Read the full description at leidos.wd5.myworkdayjobs.com. FewerJobs shows a short excerpt and links to the source.