Design Verification Engineer (Senior/Staff)

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Senior From the posting source

Schedule

Shift type

Not verified

Weekend work

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Company

Equity

Offered Verified - SEC 10-K source

Application

Cover letter

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Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Design Verification Engineer (Senior/Staff) Bayan Lepas, Penang, UNAVAILABLE, MY Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for. Responsibilities & Skills Lattice Semiconductor is seeking a Design Verification Engineer to join the RnD organization.This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow. Responsibilities & Skills: We are seeking a IP DV engineer with significant hands-on experience in pre-silicon Design verification, verification methodologies and UVM/OVM. Develop and Review Test Plan based on design specification Develop constrained-Random verification environment for complex DUT Implement coverage metrics using cover po

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