Sr. CPU Logic Design Front end Methodology Engineer

Verified benefits

Parental leave

12 weeks

Non-birth-parent leave

12 weeks

Verified

Yes last checked unknown

Salary

Not disclosed

401(k) match

Not verified

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Sr. CPU Logic Design Front end Methodology Engineer 3 Locations Sr. CPU Logic Design Front end Methodology Engineer /job/US-Texas-Austin/Sr-CPU-Logic-Design-Front-end-Methodology-Engineer_JR0281531 3 Locations Posted 30+ Days Ago

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