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SOC Physical Design Static Timing Analysis Engineer

Intel - 2 Locations

Posted Apr 28, 2026

Verified benefits

Parental leave
12 weeks
Non-birth-parent leave
12 weeks
Verified
Yes last checked unknown
Salary
Not disclosed
401(k) match
Not verified

Market context

Median wage (BLS OEWS)
$66,396 national median
Projected growth (BLS Employment Projections)
+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

SOC Physical Design Static Timing Analysis Engineer 2 Locations SOC Physical Design Static Timing Analysis Engineer /job/US-Arizona-Phoenix/SOC-Physical-Design-Static-Timing-Analysis-Engineer_JR0283411 2 Locations Posted 8 Days Ago

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