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Senior Photonic-Integrated-Circuit Engineer

Intel - US, California, Santa Clara

Posted Apr 5, 2026

Verified benefits

Parental leave
12 weeks source
Non-birth-parent leave
12 weeks
Verified
Yes last checked unknown
Salary
Not disclosed

Where they hire

State eligibility is not yet verified.

About this role

Senior Photonic-Integrated-Circuit Engineer US, California, Santa Clara Senior Photonic-Integrated-Circuit Engineer /job/US-California-Santa-Clara/Senior-Photonic-Integrated-Circuit-Engineer_JR0280862-1 US, California, Santa Clara Posted 30+ Days Ago

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