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Graduate Talent (IP Design Verification Engineer)

Intel - 2 Locations

Posted Apr 30, 2026

Verified benefits

Parental leave
12 weeks
Non-birth-parent leave
12 weeks
Verified
Yes last checked unknown
Salary
Not disclosed
401(k) match
Not verified

Market context

Median wage (BLS OEWS)
$66,396 national median
Projected growth (BLS Employment Projections)
+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Graduate Talent (IP Design Verification Engineer) 2 Locations Graduate Talent (IP Design Verification Engineer) /job/Malaysia-Penang/JR0283612-Graduate-Talent--IP-Design-Verification-Engineer-_JR0283612 2 Locations Posted 6 Days Ago

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