CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG)

Verified benefits

Parental leave

12 weeks

Non-birth-parent leave

12 weeks

Verified

Yes last checked unknown

Salary

Not disclosed

401(k) match

Not verified

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG) 2 Locations CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG) /job/Malaysia-Penang/CPU-SoC-Mask-Layout-Designer--Diploma-Level-Contract-role----Silicon-Engineering-Group--SiG-_JR0282134-1 2

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