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Clocking / Physical Design Engineer

Intel - US, Texas, Austin

Posted May 2, 2026

Verified benefits

Parental leave
12 weeks
Non-birth-parent leave
12 weeks
Verified
Yes last checked unknown
Salary
Not disclosed
401(k) match
Not verified

Market context

Median wage (BLS OEWS)
$66,396 national median
Projected growth (BLS Employment Projections)
+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Clocking / Physical Design Engineer US, Texas, Austin Clocking / Physical Design Engineer /job/US-Texas-Austin/Clocking---Physical-Design-Engineer_JR0283699 US, Texas, Austin Posted 4 Days Ago

Read the full description at intel.wd1.myworkdayjobs.com. FewerJobs shows a source-linked preview and links to the original posting.

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