CAD Engineer for CPU Logic Design and Validation

Verified benefits

Parental leave

12 weeks source

Non-birth-parent leave

12 weeks

Verified

Yes last checked unknown

Salary

Not disclosed

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

CAD Engineer for CPU Logic Design and Validation US, Texas, Austin CAD Engineer for CPU Logic Design and Validation /job/US-Texas-Austin/CAD-Engineer-for-CPU-Logic-Design-and-Validation_JR0282920 US, Texas, Austin Posted 22 Days Ago

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