FPGA Engineer - Radio & Communications

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified

Salary

Not verified

Was this benefit information wrong? Tell us.

Market context

Median wage (BLS OEWS)

$111,944 national median

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

FPGA Engineer - Radio & Communications Paris, Île-de-France, France About Us Harmattan AI is a next-generation defense prime building autonomous and scalable defense systems. Following the close of a $200M Series B, valuing the company at $1.4 billion, we are expanding our teams and capabilities to deliver mission-critical systems to allied forces. Our work is guided by clear values: building technologies with real-world impact, pursuing excellence in everything we do, setting ambitious goals, and taking on the hardest technical challenges. We operate in a demanding environment where rigor, ownership, and execution are expected. About the Role As an FPGA Radio Engineer, you will be responsible for designing and implementing the communications link between our drones and ground stations. You will work closely with our hardware and embedded software teams, taking full end-to-end ownership of the RF signal-processing pipeline - from early architecture through to production-ready deployment. This role is ideal for a highly autonomous engineer who is comfortable making system-level decisions and driving them forward in a fast-paced, demanding environment. Responsibilities - Lead the architecture and design of low-latency FPGA-based communications pipelines, spanning the entire signal chain: modulation/demodulation (e.g., OFDM, QAM), FFT, channel coding and decoding (e.g., LDPC, Turbo, Viterbi), synchronization, equalization, and link adaptation. - Own the complete FPGA development cycle, from feasibility assessment and architectural decisions to RTL implementation, simulation, verification, and deployment of robust, production-ready designs. - Conduct system-level link budget analysis, waveform simulations, and performance modeling to validate design choices and assess real-world performance under noise,

Read the full description at jobs.ashbyhq.com. FewerJobs shows a source-linked preview and links to the original posting.