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FPGA Engineer - Radar Signal Processing

Harmattan AI - Paris, Île-de-France, France

Posted Mar 17, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
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Mental health support
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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
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Weekend work
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Company

Company stage
Series B From the posting source checked Jun 20, 2026

Application

Cover letter
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Assessment
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Deadline
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Where they hire

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About this role

FPGA Engineer - Radar Signal Processing Paris, Île-de-France, France About Us Harmattan AI is a next-generation defense prime building autonomous and scalable defense systems. Following the close of a $200M Series B, valuing the company at $1.4 billion, we are expanding our teams and capabilities to deliver mission-critical systems to allied forces. Our work is guided by clear values: building technologies with real-world impact, pursuing excellence in everything we do, setting ambitious goals, and taking on the hardest technical challenges. We operate in a demanding environment where rigor, ownership, and execution are expected. About the Role As an FPGA Radar Engineer, you will help design and implement the real-time radar signal-processing pipeline that powers our drone sensing capabilities. You will work closely with hardware and embedded software engineers and be involved throughout the development cycle, from architecture and RTL implementation to integration and field validation. This role is ideal for an engineer with a strong background in DSP, practical FPGA experience, and a genuine interest in radar systems. Responsibilities - Develop FPGA-based radar signal-processing pipelines, encompassing key stages such as pulse compression, Range/Doppler processing, CFAR detection, and target tracking handoff. - Contribute to the RTL implementation of radar waveform generation and reception, including both FMCW and pulsed waveforms. - Perform system-level radar simulations, including Range-Doppler maps, SNR modeling, clutter analysis, and assessment of detection performance under realistic conditions. - Write and maintain testbenches and validation frameworks tailored to radar processing chains, enabling rapid debugging and iteration. - Collaborate closely with

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