TPU PCIe RTL Design Engineer

Verified benefits

Parental leave

18 weeks source

Non-birth-parent leave

18 weeks

Verified

Yes last checked 2026-05-07

Salary

$163K-$237K

401(k) match

Not verified

Market context

Median wage (BLS OEWS)

$116,543 national median

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

72% above the BLS national median for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

TPU PCIe RTL Design Engineer Sunnyvale, CA, USA In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU

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