Silicon RTL Design Engineer, PhD, Early Career

Verified benefits

Parental leave

18 weeks source

Non-birth-parent leave

18 weeks

Verified

Yes last checked 2026-05-07

Salary

Not disclosed

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Silicon RTL Design Engineer, PhD, Early Career Bengaluru, Karnataka, India In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive Tensor

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