Senior CPU Design Verification Engineer, Silicon

Verified benefits

Parental leave

18 weeks source

Non-birth-parent leave

18 weeks

Verified

Yes last checked 2026-05-07

Salary

$163K-$237K

401(k) match

Not verified

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

201% above the BLS national median for design aggregate.

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Senior CPU Design Verification Engineer, Silicon Mountain View, CA, USA; +3 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's

Read the full description at www.google.com. FewerJobs shows a source-linked preview and links to the original posting.