Low Power Design Methodology and Optimization Engineer

Benefits

Parental leave

18 weeks Verified - employer source source checked May 7, 2026

Non-birth-parent leave

18 weeks Verified - employer source source checked May 7, 2026

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Source-linked checked May 7, 2026

Salary

$163K-$237K not verified - source not recorded; timestamp not recorded

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

79% above the BLS role benchmark for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Low Power Design Methodology and Optimization Engineer Austin, TX, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Develop and implement advanced low power design methodologies for CPU architectures. Perform detailed power analysis, estimation, and optimization across various design stages. Collaborate with RTL design, verification, and physical design teams to integrate power-saving features. Drive the adoption of innovative power reduction techniques and tools. Contribute to the definition and validation of power management specifications. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in CPU low power design and optimization. Experience with power analysis tools, power intent formats (UPF/CPF), and power reduction techniques. Experience with

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