Integrated Circuit Package Design Engineer

Benefits

Parental leave

18 weeks From the posting source

Non-birth-parent leave

18 weeks From the posting source

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Source-linked checked May 7, 2026

Salary

$163K-$237K From the posting source

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

79% above the BLS role benchmark for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Mid From the posting source

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Integrated Circuit Package Design Engineer Sunnyvale, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Chip Package Designer, you will develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for Machine Learning (ML) chips. This involves collaborating with SI/PI, thermal/mechanical, assembly, and PCB engineers to create complex, high-performance substrate designs. You will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation. Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline. This contributes to successful chip deployment in data centers, ensuring the best optimized power, performance, area (PPA) designs and enhancing system performance relative to total cost of ownership (TCO ). Our team is responsible for designing and building the custom hardware, software, and networking technologies that power all of Google's services, as standard off-the-shelf hardware cannot meet our unique computational needs. You will be developing and building the systems that form the core of the world's largest and most powerful computing infrastructure. Your work will span from the fundamental levels of circuit design up to system design, seeing systems through to high-volume manufacturing, which directly influences the machinery in our

Read the full description at www.google.com. FewerJobs shows a preview and links to the original posting.