Circuit Design Engineer, Technology and Foundry Interface

Verified benefits

Parental leave

18 weeks source

Non-birth-parent leave

18 weeks

Verified

Yes last checked 2026-05-07

Salary

$192K-$278K

401(k) match

Not verified

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

254% above the BLS national median for design aggregate.

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Circuit Design Engineer, Technology and Foundry Interface Sunnyvale, CA, USA In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive

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