ASIC Design Verification Engineer, Platforms and Devices

Benefits

Parental leave

18 weeks From the posting source checked Jun 20, 2026

Non-birth-parent leave

18 weeks From the posting source checked Jun 20, 2026

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Source-linked checked May 7, 2026

Salary

$138K-$198K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

44% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Design Verification Engineer, Platforms and Devices Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration As a part of the Google Silicon Platforms team, you will work on verification of the backbone of Google's SOC offerings. You collaborate with hardware architects and design engineers for functional and performance verification of infrastructure IP, interconnects, caches, memory management, and system services. You will also work on developing high performance VIPs for protocols supported by our SOCs and closely collaborate on the deployment of the verification stack across a heterogeneous set of IPs. Our approach to building systems is based on scalability. Your work will include building and verifying a generalized class of system topology abstractions and developing the associated methodologies and tools needed to solve the problem. As an ASIC Design Verification Engineer, you will be part of a research and development team, and your responsibilities will include building verification components, constrained-random testing, system testing, and verification closure. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to

Read the full description at www.google.com. FewerJobs shows a preview and links to the original posting.