Senior Electrical Engineers - FPGA Design - Actively Growing Our Engineering Teams!

Verified benefits

Parental leave

4 weeks source

Non-birth-parent leave

4 weeks

Verified

Yes last checked 2026-05-07

Salary

$87K-$165K

401(k) match

Not verified

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

90% above the BLS national median for design aggregate.

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Senior Electrical Engineers - FPGA Design - Actively Growing Our Engineering Teams! US-AZ-TUCSON-M02 ~ 1151 E Hermans Rd ~ BLDG M02 Date Posted: 2026-04-01 Country: United States of America Location:

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