FPGA Design Engineer (m/f/d)

Verified benefits

Parental leave

10 weeks source

Non-birth-parent leave

10 weeks

Verified

Yes last checked 2026-05-07

Salary

Not disclosed

401(k) match

Not verified

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

FPGA Design Engineer (m/f/d) Berlin Job Description Summary As innovators in advanced power conversion and storage systems, we support our utility and industrial customers by solving their toughest electrification challenges

Read the full description at gevernova.wd5.myworkdayjobs.com. FewerJobs shows a source-linked preview and links to the original posting.