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Emulation Engineer

Etched - San Jose, CA, United States

Posted Jun 1, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
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Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
Offered From the posting source checked Jun 20, 2026
Relocation assistance
Not verified
Childcare support
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Learning budget
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Verification
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Salary
$150K-$275K From the posting source checked Jun 20, 2026
401(k) match
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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

82% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
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Weekend work
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Company

Company stage
Growth-stage From the posting source checked Jun 20, 2026

Application

Cover letter
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Assessment
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Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Emulation Engineer San Jose, CA, United States About Etched Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Key responsibilities - Oversee SoC bring-up on emulation platforms; diagnose and resolve failing SoC/processor tests. - Develop and maintain automated build and regression flows to accelerate pre-silicon validation and software development. - Provide support across emulation environments using advanced techniques including C/C++ DPI transactors, coverage analysis, and in-circuit emulation for high-speed protocols. - Collaborate closely with Design, DV, Silicon Validation, Performance, and Software teams, and partner with leading emulation vendors to enhance platform capabilities and resolve complex issues. - Develop high-performance infrastructure to capture debugging signals and surface actionable insights for users. - Implement hybrid emulation environments using custom DPI-based streaming transactors. - Create highly configurable chip-to-chip network models using emulation-efficient primitives. - Build and maintain CI pipelines and git-based workflows for emulation build reproducibility and regression tracking. You may be a good fit if you have - Hands-on experience with emulation platforms such as Palladium, Protium, Veloce, ZeBu, or HAPS, covering design bring-up, build flows, debugging, and performance tuning. - Strong C/C++ and Linux system development skills. Proficiency with SystemVerilog and Verilog, including DPI-based interfaces. - Experience with git-based development workflows

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