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Design Verification Engineer - Internal IP

Etched - Austin

Posted Apr 16, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
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  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
Offered From the posting source checked Jun 20, 2026
Relocation assistance
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Childcare support
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Learning budget
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Verification
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Salary
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401(k) match
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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
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Weekend work
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Company

Company stage
Growth-stage From the posting source checked Jun 20, 2026

Application

Cover letter
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Assessment
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Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Design Verification Engineer - Internal IP Austin About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering Sohu - including systolic arrays, DMA engines, and NoCs - are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack. Key responsibilities - Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems). - Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks. - Debug complex datapath and protocol issues in RTL and testbench environments. - Work closely with architects and designers to validate functionality and design intent. - Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage. - Contribute to reusable DV infrastructure, coverage models, and methodology improvements. You may be a good fit

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