Power Performance Architect, Senior Staff - Accelerator Design

Benefits

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Market context

Median wage (BLS OEWS)

$116,543 national median

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

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Weekend work

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About this role

Power Performance Architect, Senior Staff - Accelerator Design Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week. What You Will Do: • Responsible for pre-silicon power estimation of the blocks in design. The responsibility includes both RTL power estimation as well as Physical design power estimation of the blocks. • You will work with front-end and DV engineers to identify the windows of power activity in the design. You will work with the RTL team to ensure that the feedback from the estimation is implemented and results in optimizing power. • Build an architectural power estimation tool for AI workloads to compute power based on system configuration and die level metrics. This will include workload profiling using external/internal memory size, bandwidth, gate counts, of compute/memory blocks. • You will work with frontend architects and backend design to compile the performance monitor availability,

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