STA CAD/Methodology Engineer

Benefits

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Verification

Not verified last checked Jun 13, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Weekend work

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Application

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About this role

STA CAD/Methodology Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands-on with the Physical Design of intricate chip partitions. Your Impact This role as a Static Timing Analysis (STA) CAD/Methodology Engineer on Cisco's Silicon One Engineering team offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs. You will lead the development of scalable STA flows and automation, enhancing the efficiency and quality of design processes. Working at the intersection of design, methodology, and infrastructure, you will help establish best practices and drive innovation within a leading silicon organization. Contribute to the development, maintenance, and automation of STA signoff flows for complex SoC designs. Assist with timing constraint development (SDC) and validation for multi-mode, multi-corner analysis. Develop and enhance automation scripts and utilities (TCL, Python) to streamline timing flows and improve engineering efficiency. Work with senior engineers to support timing closure during the design cycle, assisting with debug and issue triage. Collaborate with RTL, DFT, and physical design teams to align on design intent and STA best

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