Senior Signal and Power Integrity Enginee

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

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Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Senior Signal and Power Integrity Enginee Bangalore, India Meet the Team At Cisco, Bangalore, the Common Hardware Group (CHG) architects, designs, builds, and delivers world-class Access, Edge, Aggregation, and Core routers that cater to the growing bandwidth demands of leading service providers and large enterprises. Your Impact As Senior Signal and Power Integrity Engineer in this team of outstanding engineers from a diverse group of backgrounds, you will: Be responsible for delivering system-level signal and power integrity solutions for large sophisticated high-speed systems, boards & packages. Develop SI rules, review design implementation, build test plans, and document characterization & measurement reports. Improve & optimize design margins through interconnect, timing and crosstalk analysis, 3D EM & channel simulations for high-speed designs. Design & characterize test structures & channel models to correlate simulations with measurements for Serdes and interconnects. Collaborate with multi-functional teams - HW, PCB Layout, SW, MFG, ASIC. Be responsible for electrical characterization and verification of Transmitter/Receiver SERDES settings to meet the industry standards and internal Cisco requirements. Minimum Qualifications and Expectations Bachelor's or Master's Degree in Electrical Engineering, 6+ yrs of demonstrated ability in hardware design with emphasis on Signal and Power Integrity Hands on exposure to lab measurements including real-time scope, sampling scope, Spectrum analyzer, VNA & TDR. Good understanding of EM and transmission line concepts, timing, jitter, crosstalk, noise, channel modeling, channel equalization techniques, power delivery & decoupling. Experience with 56G PAM4, 25G & 10G NRZ Serdes technologies, and DDR - simulation, bring up, debug, measurements, and

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