Senior RTL Design Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Work mode

Hybrid From the posting source checked Jun 20, 2026

In-office days

2 days From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

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Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Senior RTL Design Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team Join the Silicon One Team at Cisco in Armenia, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work firsthand with the Physical Design of intricate chip partitions. Your Impact This role offers a unique chance to shape the future of networking innovation within Cisco Silicon One. As a key technical leader, you will drive next-generation silicon architecture development, guide your team in delivering solutions that power advanced global networks, and lead collaboration across multiple teams. You will mentor engineers and influence physical design strategies that set new industry standards. Your expertise will be critical to the successful delivery and continuous improvement of Cisco's most advanced silicon solutions. Taking part in all aspects of digital design, from micro-architecture to RTL design and qualification. Sub-system/SoC integration and verification. Review/enhancement of RTL codes. Improve flows and methodologies to streamline IP/SoC development and integration. Work closely with the verification team for complex debugs to resolve verification failures. Close interaction with the physical design team to reach better physical design QoR. Minimum Qualifications 6+ years of industry experience in ASIC digital design.

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