Senior Design Verification Engineer

Verified benefits

Parental leave

13 weeks source

Non-birth-parent leave

13 weeks

Verified

Yes last checked unknown

Salary

Not disclosed

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Senior Design Verification Engineer Belgrade, Serbia Meet the Team Join our SiliconOne team in Serbia, specializing in ASIC functional verification for Cisco Silicon One chips—high-performance networking chips utilized by major

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a short excerpt and links to the source.