Senior ASIC Physical Design Technical Lead

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$211K-$305K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

121% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Senior ASIC Physical Design Technical Lead San Jose, California, US The application window is expected to close on: 07/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco's core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One-the industry's only unified silicon architecture spanning top-of-rack switches to web-scale data centers-you'll help shape Cisco's groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry. Your Impact Fullchip Floorplan by understanding the architecture of the design and IP placement constraints Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization. Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements. Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology. Proficiency in low-power design methodologies using UPF Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive

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