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MBIST Design Engineer

Cisco - Armenia

Posted May 12, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
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Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
Not verified last checked Jun 13, 2026
Salary
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401(k) match
Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Schedule

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Weekend work
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Application

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Deadline
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Where they hire

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About this role

MBIST Design Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team Join Cisco's ASIC Design for Test (DFT) Team, where innovation, collaboration, and technical excellence drive everything we do. As a group of passionate engineers, we are committed to pushing the boundaries of testability and reliability in complex silicon systems. Our mission is to enable robust, high-quality silicon by architecting and implementing advanced DFT solutions. Working in close partnership with design, verification, and physical implementation teams, we ensure that every Cisco chip is not only powerful, but also rigorously tested and dependable. Here, you'll play a pivotal role in shaping the future of test engineering while growing alongside some of the best minds in the industry. Your Impact In this role, you will be central to Cisco's silicon quality and innovation by developing advanced DFT strategies that ensure every chip meets the highest standards for testability and reliability. You will address challenges across digital and mixed-signal domains, collaborating with multi-functional teams to design, implement, and optimize sophisticated test solutions. Your work will enhance product robustness, accelerate silicon validation, and drive progress in automated test methodologies. Architect and Implement DFT Solutions: Design and integrate advanced Test Access Mechanisms (TAM), scan chains, Built-In Self-Test (BIST), and Memory BIST (MBIST) infrastructures for complex integrated circuits. Test Planning and Coverage Analysis: Lead test planning, test pattern generation, and fault coverage analysis to improve test coverage for both digital and mixed-signal designs. Collaborate Across Teams:

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Apply link verified; last checked Jun 13, 2026.

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