MBIST Design Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Work mode

Hybrid From the posting source checked Jun 20, 2026

In-office days

2 days From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

MBIST Design Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team Join Cisco's ASIC Design for Test (DFT) Team, where innovation, collaboration, and technical excellence drive everything we do. As a group of passionate engineers, we are committed to pushing the boundaries of testability and reliability in complex silicon systems. Our mission is to enable robust, high-quality silicon by architecting and implementing advanced DFT solutions. Working in close partnership with design, verification, and physical implementation teams, we ensure that every Cisco chip is not only powerful, but also rigorously tested and dependable. Here, you'll play a pivotal role in shaping the future of test engineering while growing alongside some of the best minds in the industry. Your Impact In this role, you will be central to Cisco's silicon quality and innovation by developing advanced DFT strategies that ensure every chip meets the highest standards for testability and reliability. You will address challenges across digital and mixed-signal domains, collaborating with multi-functional teams to design, implement, and optimize sophisticated test solutions. Your work will enhance product robustness, accelerate silicon validation, and drive progress in automated test methodologies. Architect and Implement DFT Solutions: Design and integrate advanced Test Access Mechanisms (TAM), scan chains, Built-In Self-Test (BIST), and Memory BIST (MBIST) infrastructures for complex integrated circuits. Test Planning and Coverage Analysis: Lead test planning, test pattern generation, and fault coverage analysis to improve test coverage for both digital and mixed-signal designs. Collaborate Across Teams:

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.